In a normal semiconductor memory, a plurality of pads are arranged at peripheral portions of a semiconductor chip wherein memory cells and the like are formed. These pads are connected to inner leads via bonding wires constituting transfer paths of signals from the outside of the chip.
In recent years, when a speedup requirement of access time is enhanced, a memory cell array is divided into a plurality of core blocks. In such a chip of a semiconductor memory, the speedup requirement cannot fully be met by a conventional pad allocation wherein the length of wirings is apt to cause delay.
An allocation wherein pads are provided at the central portion of the chip in rows (hereinafter, center pad allocation) may be considered as a method of resolving the above-mentioned problem. However, when this center pad allocation is used, the wirings are concentrated in the central portion of the chip whereby efficient wirings become very difficult.
As explained above, in the conventional semiconductor memory, pads are arranged at the peripheral portions of the chip, and therefore, the length of signal lines is apt to cause delay which makes speedup more difficult. When center pad allocation is used to meet the above-mentioned problem, the wirings are concentrated in the central portion of the chip whereby efficient wirings become very difficult.